module insn_mem_top_tb ();
  
  reg clk,rst;
  reg [31:0] insn_Address;
  
  wire [31:0] insn;



insn_mem_top U1(clk,rst,insn_Address,insn);

  // initial #200 $finish;
    initial begin
    clk=1;  
    rst=0; 
    insn_Address = 32'b00000000000000000000000000000100;
    forever #10 clk=~clk; 
    end 
    
    initial begin    
    #20;
    insn_Address = 32'b00000000000000000000000000000100; #20;
    
    insn_Address = 32'b00000000000000000000000000001000; #20;
   
    insn_Address = 32'b00000000000000000000000000001100; #20;
   
    insn_Address = 32'b00000000000000000000000000010000; #20;
   
    insn_Address = 32'b0000000000000000000000000010100; #20;
   
    insn_Address = 32'b0000000000000000000000000011000; #20;
   
    insn_Address = 32'b00000000000000000000000000011100; #20;
   
    insn_Address = 32'b00000000000000000000000000100000; #20;

    $stop;
  end

  endmodule
    